1 note: this is a summary docu ment. a complete document is available under nda. for more information, please contact your local atmel sales office. features ? compliant with trusted computing group (t cg) trusted platform module (tpm) main specification version 1.2 compliant with tcg pc cl ient specific tpm interface specification version 1.2 single chip turnkey solution hardware asymmetric crypto engine 2048 rsa sign in 500 ms avr ? risc microprocessor 33 mhz lpc (low pin count) bus for easy pc interface secure hardware and firmware design true random number generato r (rng) ? fips 140.2 compliant secure real-time clock option 3.3v 10% supply voltage 28-lead tssop package or 40-lead qfn package 0?70 c temperature range description the at97sc3203 trusted platform module (tpm) is the latest offering from atmel, the world's leading choice for tpms. atmel, supplier of the world's first production v1.1b tpm, the at97sc3201, expands its success into v1.2 tpms with the at97sc3203. atmel continues to pace the development of tpm technology and actively participates in the trusted computing group (tcg) and contributes expertise in the development of the tpm specificat ions. by utilizing atmel tpms, you can be confident that you are implementing the most advanced tpms available on the market today and in the future. the at97sc3203 is a fully integrated security module designed to be integrated into personal computers and othe r embedded systems. it implements version 1.2 of the trusted computing group specification for trusted platform modules. the tpm includes a cryptographic accelerator capable of computing a 2048-bit rsa signature in 500 ms and a 1024-bit rsa signature in 100 ms. performance of the sha-1 accelerator is l50 s per 64-byte block. in most cases, tcg key generation operations will be completed using a proprietary mechan ism in less than 1 msec. the chip communicates with the pc through the lpc interface. the tpm supports sirq (for interrupts) and clkrun to perm it clock stopping for power savings in mobile computers. trusted platform module at97sc3203 summary advance information rev. 5116as-tpm?7/05
2 at97sc3203 5116as-tpm?7/05 figure 1. at97sc3203 block diagram figure 2. atmel at97sc3203 tpm pin configuration 33 mhz lpc interface avr? 8/16 bit cpu physical security circuitry gpio rtc v bb 32.768 khz rng timer rom program eeprom program eeprom data crypto engine sram gpio6 nc nc nc gnd s b 3 v gpio6 nc te s ti te s tbi/badd 3 v gnd vbat xt a li/ 3 2k in xt a lo 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 2 8 27 26 25 24 2 3 22 21 20 19 1 8 17 16 15 lpcpd# s erirq lad0 gnd 3 v lad1 lframe# lclk lad2 3 v gnd lad 3 lre s et# clkrun 2 8 pin t ss op 9.6 mm, 0.65 mm pitch 6.1 mm pl as tic width 40 pin qfn 6.0 mm x 6.0 mm 0.50 mm pitch nc nc nc nc nc nc nc nc lpcpd# s erirq nc xtali/ 3 2k in xtalo nc nc nc nc nc clkrun# lre s et# nc gnd s b 3 v gpio6 nc te s ti te s tbi/badd 3 v gnd vbat lad0 gnd 3 v lad1 lframe# lclk lad2 3 v gnd lad 3 1 2 3 4 5 6 7 8 9 10 3 0 29 2 8 27 26 25 24 2 3 22 21 11 12 1 3 14 15 16 17 1 8 19 20 40 3 9 38 3 7 3 6 3 5 3 4 33 3 2 3 1
3 at97sc3203 5116as-tpm?7/05 table 1. pin descriptions name tssop pin # qfn pin # type description lad[3:0] 17, 20, 23, 26 30, 27, 24, 21 input or output lpc multiplexed command, address, data: internal pull-ups are provided. lframe# 22 26 input lpc frame: indicates th e start of an lpc cycle, or an abort. lpcpd# 28 32 input power down: indicates that the tpm should prepare for power to be shut off on the lpc interface. if this pin is unused, it should be tied to the 3v power supply pin through a resistor. clkrun# 15 19 input or output pci clock run: active low output enabling the system lpc clock. if this pin is unused, it should be tied to ground. lclk 21 25 input 33mhz pci clock provides timing for all transactions on the pci bus. lreset# 16 20 input pci signal to reset all devices that reside on the pci bus. serirq 27 31 input or output serialized interrupt request signal. if the serirq function is enabled, this pin should be connected to the cpu serirq input, and the line pulled to the 3v power supply pin through a resistor. if this pin is unused, it should be tied to the 3v power supply pin through a resistor. sb3v 5 3 input standby 3.3v supply. if no separate standby power supply is connected to this pin, the pin should be tied directly to the 3v power supply pin. 3v 10, 19, 24 8, 23, 28 input primary 3.3v dc power supply input rail supplied by the motherboard. may be referred to as vcc. gnd 4, 11, 18, 25 2, 9, 22, 29 input system ground. nc 1 39 output no connect. this pin may be floated. if the xor chain i/o test mode is used, the pin should be tied to ground directly or through a resistor. reserved for the smbus data i/o function. nc 2 40 output no connect. this pin may be floated. if the xor chain i/o test mode is used, the pin should be tied to ground directly or through a resistor. reserved for the smbus clock input function. vnc 3 1 output vendor no connect, as designated in the pc client tis specification. this pin may be fl oated. if the xor chain i/o test mode is used, the pin should be tied to ground directly or through a resistor. gpio6 6 4 input or output general purpose input/output. intern al pull-up resistor. this pin is mapped to nv index tpm_nv_index_gpio_00 and serves as the gpio-express-00. default tpm configuration: gpio input. gpio6 also serves as the xor chain output during i/o test mode. nc75input no connect. this input pin has an internal pull-down resistor and may be floated. if the xor chain i/o test mode is used, the pin should be tied to the 3v power supply directly or through a resistor. testi 8 6 output tpm manufacturing test input disabled. this pin may be floated. if the xor chain i/o test mode is us ed, the pin should be tied directly to ground. testbi/badd 9 7 input testbi and badd functions disabled. this pin should be tied directly to ground.
4 at97sc3203 5116as-tpm?7/05 absolute maximum ratings (preliminary) notes: 1. these parameters guaranteed by design. vbat1210input 3.3v battery input. if no external battery is connected to this pin, the pin should be tied directly to the 3v power supply pin. xtali/32k in 13 12 input 32 khz crystal oscillator input or 32 khz clock input. this pin should be tied to ground if not used. xtalo 14 13 output 32 khz crystal oscillator output. operating temperature..............................0c to +70c storage temperature (without bias)...........0c to + 70c voltage on i/o pins.............................. ? 0.1 to v cc +0.3v voltage on vcc with respect to ground.................6.0v maximum esd voltage..........................................2000v *notice: stresses beyond those listed under ? absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification may cause temporary or permanent failure. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. dc parameters (preliminary) vcc = 3.0 to 3.6v; temperature = 0 to 70c symbol parameter min nom max units notes vcc supply voltage 3.0 3.3 3.6 v icc operating current at fclk = 33 mhz 25 50 ma ist static current 5 10 ma vcc =3.6v; fxtal = 0 hz; active inputs isl sleep current, chip idle 40 100 a vcc = 3.6v; fxtal = 0 hz ibb battery current 2 4 a vcc = 0v; fxtal = 0 hz ilio input leakage 0.1 3 a vin = vcc or gnd vih input high threshold 0.5 * vcc 0.5 + vcc v vil input low threshold -0.5 0.3 * vcc v voh output high voltage 0.9 * vcc 0.98 * vcc v at iout = ?500 a vol output low voltage 0.1 * vcc v v at iout = 1.5 ma iolcr output low current, clkrun# 7 ma at vout = .615 * vcc ci input pin capacitance 6 pf note 1 table 1. pin descriptions (continued) name tssop pin # qfn pin # type description
5 at97sc3203 5116as-tpm?7/05 notes: 1. these parameters guaranteed by design. 2. all parameters measured with respect to signal crossing vtest = 0.4 * vcc unless otherwise noted. 3. the minimum parameter must never be violated under any ci rcumstances unless lreset# is asserted. if proper clkrun# signaling is observed, the maximum specification can be violated. notes: 1. current as of publication date. contact atmel marketing for status update. 2. also rohs table 3. ac parameters cl = 10pf.; vcc = 3.0 to 3.7v; temperature = 0 to 70-c symbol parameter min nom max units notes tval clk to signal valid delay ? lad0-3 2 5 11 ns measured at vtrise = 0.285 * vcc and vtfal = 0.615 * vcc. measured from clk at vtest = 0.4* vcc; load = 200. ton float to active delay 2 4 ns toff active to float delay 28 ns tsu input setup time to clk 7 2 ns th input hold time from clk 0 ?500 ns trst reset active time af ter power stable 1 ms note 1 trst- clk reset active after cl k stable 100 ms note 1 trst- off reset active to output float delay 40 ns note 1 tclkin clk period 29.5 30 31 ns note 3 tclkl o clk low duration 13.4 18 ns note 2, note 3 tclkhi clk high duration 13.4 18 ns note 2, note 3 table 4. ordering information ordering code (1) package operation range at97sc3203-01ac 28a3 (tssop) commercial (0 to 70 c) at97sc3203-x1ac 28a3 (tssop) lead-free (2) commercial (0 to 70 c) at97sc3203-01mc 40ml1 (qfn) commercial (0 to 70 c) AT97SC3203-X1MC 40ml1 (qfn) lead-free (2) commercial (0 to 70 c)
6 at97sc3203 5116as-tpm?7/05 package drawing 28a3 ? tssop 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 1/ 8 /02 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d 9.60 9.70 9. 8 0 2, 5 e 8 .10 b s c e1 6.00 6.10 6.20 3 , 5 a ? ? 1.20 a2 0. 8 0 1.00 1.05 b 0.19 ? 0. 3 0 4 e 0.65 b s c l 0.45 0.60 0.75 l1 1.00 ref 2 8 a 3 , 2 8 -le a d, 6.1 x 9.7 mm body, 0.65 pitch, thin s hrink s m a ll o u tline p a ck a ge (t ss op) note s : 1. thi s dr a wing i s for gener a l inform a tion only. ple as e refer to jedec dr a wing mo-15 3 , v a ri a tion db for a ddition a l inform a tion. 2. dimen s ion d doe s not incl u de mold fl as h, protr us ion s or g a te bu rr s . mold fl as h, protr us ion s a nd g a te bu rr s s h a ll not exceed 0.15 mm (0.006 in) per s ide. 3 . dimen s ion e1 doe s not incl u de inter-le a d fl as h or protr us ion s . inter-le a d fl as h a nd protr us ion s s h a ll not exceed 0.25 mm (0.010 in) per s ide. 4. dimen s ion b doe s not incl u de d a m ba r protr us ion. allow ab le d a m ba r protr us ion s h a ll b e 0.0 8 mm tot a l in exce ss of the b dimen s ion a t m a xim u m m a teri a l condition. d a m ba r c a nnot b e loc a ted on the lower r a di us of the foot. minim u m s p a ce b etween protr us ion a nd a dj a cent le a d i s 0.07 mm. 5. dimen s ion d a nd e1 to b e determined a t d a t u m pl a ne h. 2 8 a 3 a l1 a l d a2 e e1 e b top view s ide view end view
7 at97sc3203 5116as-tpm?7/05 40ml1 ? qfn 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. a1 a3 a a2 0 side view 40ml1 , 40-lead 6.0 x 6.0 mm body, 0.50 mm pitch, molded quad flat no lead package (mlf2) a 40ml1 3/9/04 notes: 1. this drawing is for general information only. refer to jedec drawing mo-220, variation wjjd-2, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. common dimensions (unit of measure = mm) symbol min nom max note d 6.00 bsc e 6.00 bsc d2 3.95 4.10 4.25 e2 3.95 4.10 4.25 a - 0.85 0.90 a1 0.0 0.01 0.05 a2 - 0.65 0.70 a3 0.20 ref l 0.30 0.40 0.50 e 0.50 bsc b 0.18 0.23 0.30 2 d e top view n 2 3 1 pin 1 indicator l pin1 id b n d2 3 2 1 e bottom view e2
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